The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, such as p-channel MOS (PMOS), n-channel MOS (NMOS) and complimentary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors, etc.
Each of these semiconductor devices generally include a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistors, an active device generally includes source and drain regions and a gate electrode which modulates current between the source and drain regions.
One important step in the manufacture of such devices is the formation of isolation areas to electrically separate electrical devices, or portions thereof, that are closely integrated in the silicon wafer. While the particular structure of a given active device can vary between device types, a MOS-type transistor generally includes source and drain regions and a gate electrode that modulates current flowing in a channel between the source and drain regions. Current should not flow between source and drain regions of adjacent MOS-type transistors. However, during the manufacturing process movement of dopant atoms, for example, of boron, phosphorus, arsenic or antimony, can occur within the solid silicon of the wafer. This movement is referred to as diffusion. The diffusion process occurs at elevated temperatures where there is a concentration gradient between dopant atoms external to the silicon wafer and dopant atoms diffusing into the silicon wafer and is typically employed when forming p-type and n-type regions of a silicon integrated circuit device.
A technique referred to as "trench isolation" has been used to limit such flow. A particular type of trench isolation is referred to as shallow trench isolation (STI). STI is often used to separate the respective diffusion regions of devices of the same polarity type (i.e., p-type versus n-type).
Another important step in the manufacture of such devices is the formation of load devices. Load devices are constructed to provide a selected degree of electrical resistance between two or more electrical components or regions. As an example, a terminal of an electrical component can be "pulled up" to a power source through a load device. Pulling up the component in this manner biases the component so that the voltage at its terminal follows the voltage of the power source in the absence of another force directing the terminal toward another voltage. In MOS-based circuits, load devices are commonly implemented using one or more PMOS or NMOS transistor, with the source-drain channel used to provide the resistance.
For many applications, using large-sized loads is desirable, because the size of the load is proportional to the amount of electrical resistance provided between the terminal and the power source. Using the example application above, a large-size load thereby permits a smaller force to direct the terminal of the electrical component toward the other voltage that is at a level different than the voltage level of the power source.
In many applications, STI regions and load devices consume a significant amount of real estate and are quite common. Consider, for example, a static memory access memory (SRAM) cell which uses multiple STI regions and load devices. Typically, an SRAM is implemented as an array including thousands of memory cells. The amount of real estate consumed by the STI regions and load devices through the SRAM array is quantified by multiplying the amount of real estate consumed in each cell by the total number of cells in the array.
With the demands for increasing the density of such MOS-based circuits continuing to escalate, there is an ongoing need to reduce the amount of real estate consumed by various aspects of the circuits, such as regions occupied by STI and load device structures.